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Microelectronics: Fabrication of micro/nano structures on silicon surface

In microelectronics, fabrication of metal structures (micro/nano) are state-of-art research due to their broad range of applications. On of the major application of microfabrication is the production of thin-film transistors (TFTs). In one of the production process of TFT is by depositing metal structures on the silicon wafer (i.e. above the insulator layer). Channel region between these metal structures is the region where semiconductor is deposited to produce a working field-effect TFT. Major interest for scientists all over the world is the production of large area printable, low-cost and low-temperature processable TFTs. For the production of low-cost TFTs, the fabrication technique too demands cheaper and the faster processes. Phot0lithograpy is such a cheaper and faster process, that yields TFTs with channel length down to 1um. However, the process is unreliable in nanometre scale. For futher, below 1 um e-beam lithography is applied. E-beam lithograpy is very reliable, yields the TFT with channel in the orders of nanometers. But, the process is expensive and slow. For sub-100 nm shadow based deposition is also beneficial. However, this is rather cubersome process and needs highly-skilled manpower. Apart from transistors, these structures could be also applied as the sensors and the thin micro/nano fluidic-channel in the field of Lab-on-Chip Technology, plamonics for Surface Enhancement in thin film Solar Cells, Surface analysis esp. in Surface Enhanced Raman Scattering Measurement e.t.c.


(1) Photolithography

Term photolithography could be separated into two parts-photo (application of light) and lithography (depositon of metal). Lithography carried out by the application of light source is photolithography. The basic steps necessary for the photolithograpy is depicted in figure (1). This lithography process is divided into six different sub-processes. The first step is termed as development. In this step-the light soucre must be high energy sufficient to break the long-chain of resist polymer into shorter length such that they easily dissolve in the developer solution. Hence, UV (Ultraviolet) light is directly applied above the mask onto the e-beam resist layer. The mask consists of the structures which are described by the channel length (L) and the channel width (W).


Figure (1): Schematic diagram depicting six major steps in the Photolithography process.


Depending on the positive or the negative photoresist, whether exposed region dissolves into the developer solution or exposed region remains after development. e.g Az1512HS is the positive photoresist material and it dissolves easily in the Az726MIF solution. The developed sample is then fed into the metallization chamber (e-beam evaporation) and very thin layer of Ti/Au is deposited on the sample. Titanium acts as the adhesion layer between gold (Au) and the silicon dioxide. After metallization, sample is lifted-off in the acetone solution. The device structure after lift-off under optical microscope is shown in figure (2).


Figure (2): Microstructures (Au) deposited above the silicon-dioxide with certain channel length (L)and width (W), observed immediately after lift-off under optical microscope.


Further, to create structures with channel length in the orders of nanometres e-beam lithography must be carriedout. Photolithography becomes unreliable in the nanometre scale because at this length scale the incoming light refracts while passing through medium of variable refractive index. After optimization of setup it is impossible to fabricate nanostructures with photolithography. Hence, it is necessary to opt e-beam lithography process.


(2) E-beam lithography

In the e-beam lithography inspite of UV light high energy electron beam (30KeV) is applied on the e-beam resist layer inside the SEM. Similar to UV rays, high energy electron beams break the long chain polymer of e-beam resist such that they dissolves in the e-beam developer solution. Developed sample is then fed to the metallization chamber and thin layer of Ti/Au (3/17nm) lyer is deposited. Basic steps of e-beam lithography are shown in the below figure (4). Similarly, a device structure after lift-off is shown in figure (5).


Figure (3): Schematic diagram of a Scanning Electron Microscope (SEM)-A General Setup.


Figure (4) Schematic diagram of the e-beam lithography steps (1 - 6).


Figure (5): Sample structure after contact deposition and the L=1um device structure. Channel region is described by the fingures such that distance between two consecutive contact is the channel length and total channel interconnection between the contats is the chanenl width.


For the optimization of the device production, first e-beam lithography is performed. Later contacts are deposited with photolithography because contacts are relatively larger than the finger structure.



(3) Shadow based deposition

The deposition process is divided into two parts. In the first part, template metal contact (Au) is deposited on the silicon wafer with standard e-beam lithography withe size of 100um by 100um. E-beam litohgraphy is performed to ensure that the edges are sharp. In the next step another metal layer is deposited above this template such that the metal cast the shadow (region free from metal) on the insulator. The size of the shadow is the actual channel deposited. The channel length (L) can be easily tuned by tuning the angle of tilt and the height of templated metal contact. The detail shadow process and the actual device profile is shown in figure (6) and figure (7).


Figure (7): Schematic diagram of the shadow deposition technique


Figure (8): Typical shadow deposited contact for L = 70 nm structure.


With this approach, OFETs with channel length (L) down to 35 nm has been successfully fabricated. The SEM pictures are depicted in figures (8) and (9) with channel lengths L=70nm and L=35nm. However, as discussed in figure (7-c), the actual size of the channel is slightly smaller than the observed channel.


Figure (9):SEM picture of a nanostructure with Channel length of 35 nm produced by shadow based deposition process.



Intersting links:

1. Lab Course Microelectronic Fabricaiton-Intel Corp.

2. Standard Nanoelectronic Facility-Stanford University


Video1: Production of Silicon Wafers-MEMC Fabrication Facility, Texas.


Video2: How a CPU is made-AMD Electronics.




Organic Field Effect Transistors



Magnetic Memory Unit

⇒ Nano-Fabrication

⇒ Single Molecular Rectifiers

Introducton to OFETs

OFET Electrical Characterization (a, b)

Gate Field Dependent Moblity





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Last Updated on August 3rd, 2012 at 19:00 pm