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ALD: Self-terminating and Saturating gas-solid Chemical Reaction on the Substrate

ALD encorporates two: self-limiting and complementary reactions, sequentially and alternating leading to the depositing of a homogeneous and conformal layer growth. Conformal thin-film deposition is opted in the deposition of Seed Layer for Copper Interconnection, Barrier layer for preventing Cu-electromigration into the Low-K Dielectrics, Ultra-Pure Magnetic Material for Magnetic Random Access Memory (e.g. DRAM) Units (ITRS Roadmap till 2020), e.t.c. This article deals with detial investigation of ALD reaction conditions on the growth of Molelecule during the surface gas-solid surface reaction.

ALD of Al2O3 by TMA and Waters is considered as an ideal ALD process, which would be investigated by exploring the surface activities occuring during each half-cyle of ALD process. Change is growth per cycle (gpc) with different experimental conditions (esp. Pressure inside the chamber, Chamber/Substrate Temperature, Precursor/Reactant Dosing Temperures) are major highlight of this article. At the end, the results from the different ALD Process conditions are summarized to extract very important information about the ALD Window necessary for getting a perfectly homogeneous and confrmal growth of sub-monolayer film.

ALD Al2O3 by TMA and Water

Fig. 3: Self-saturating half-cycle reactions depicted by a schematic diagram for the ALD steps for Al2O3 on the Substrate by TMA (Precursor) and Water (Reactant) molecules.





Atomic Layer Deposition: An introduction and application to Micro- and Nanoelectronics

Atomic Layer Deposition is the conformal, homogeneous and surface-controlled thin-film deposition technique. ALD involves two self-limiting and complementary reactions sequentially and alternatingly for the depositing of a perfectly homogeneous and ultra-pure very thin-film. In fact, the ALD incorporates angstrom (A°) or monolayer film-deposition control possiblity.

Historically, ALD was introduced in year 1970. It used to be termed as Atomic Layer Epitaxy (ALE). Inital research on ALE was carried out by the Research Group from University of Helsinky, Finland led by Prof. Dr. Tuomo Suntola. In year 1977, Pro. Suntola filed a patent for the production of compound thin-films, which was the first patent in the development of ALD process [1]. The first pioneering research work on ALE from Prof. Suntola was published in Materials Science Reports in 1989 [2]. The inital phase of ALE was entirely dedicated towards the growth of single crystal of III-V and II-VI compounds and ordered heterostructures like superlattices and superalloys. Those days ALE was studied to meet the requirement for the improvement of ZnS thin-films and dielectric thin-films for electrolumniscent thin-film displays [3][4].


Fig. (1): Figure 3. Cross-sectional SEM image of an Al2O3 ALD film with a thickness of 300 nm on a Si-wafer with a trench structure. (Source: From ref 42. Copyright 1999 John Wiley & Sons.)




Investigation of Sub-threshold slope in Nanoscale P3HT Organic FETs (OFETs)

This article deals with the comparative analysis of sub-threshold slope parametre in the nanometre sized bottom-gate bottom-contact OFETs. The nanoOFETs are fabricated on the 58 nm silicon dioxide insulator on the n-doped silicon substrate. All the devices are fabricated by the e-beam lithography processes. For the measurement, 0.5 wt% of P3HT P200 (45 nm thin) semiconductor is spin-coated on the sample inside the glove-box (N2 and air is less than 0.5 ppm).

The study is very important in any OFET analysis because the sub-threshold property is directly related with the bulk transport characteristics of the device, since the bulk property in one hand reflects the OFF state of the device and in the other hand it gives the electrical measurement of the trapped charges within the devices. Hence, for the device sub-threshold characterization, firstly sub-threshold slope would be introduced, considering the physical significance and the importance of this parameter for the analysis of an OFET. Secondly, basic steps in calculating sub-threshold slope would be discussed concentrating on a bottom-gate bottom-contact OFETs with channel length of L = 100 nm and a L = 10 μm. Device basic transport parameter like mobility and threshold voltages would also be calculated additionally. The comparative analysis would also hint us the effect of decreasing channel length on the transport behavior. Further, the calculated sub-threshold slopt would be plotted for different channel length OFETs. Finally, comprehensive device analysis would be done from the plots.



Effect of short-channel behavior on variation of channel length in P3HT nanoOFETs

In this section, output characteristics of P3HT nanoOFETs fabricated on Silicon wafer are compared. The nanoOFETs are fabricated such that the channel length to oxide thickess (L/tox) varies between 1-10. The effect of decreasing channel length on the performance of a nanoOFET will be clearly observed as the non-saturating output curve in very small channel OFET (L=100nm) as compared to relatively larger channel OFET (L = 1 um). As discussed in very short-channel OFET with L=70nm, the output current changes non-linearly with the applied drain-potential. Smaller the channel is the probability of space charge carriers in reaching the drain contact becomes very high. Also, the potential at the drain terminal is also influenced by the potential at the source terminal, thus channel fails to pinch-off. At higher drain potential, space-charge carriers easily reach the drain terminal from the source terminal and results in the non-linear output characteristics.



Electrical Characteristics of P3HT nanoOFET (L = 70 nm)

Conventionally OFETs with channel length less then 1 um (L < 1 um) is termed as nanoOFETs. When transistor size is sufficiently small i.e. channel length is in the orders or smaller than the oxide thickness (L <= tox), transistor deviates from its normal operation and exhibits different short-channel behaviors, like: failure of drain current saturation at higher drain potential, difficult in switching OFF the transistor, higher threshold voltage, lowering of gate-effect and drain induced barrier lowering (DIBL).

Such transistors are also termed as short channel OFETs. Typical output curve of the short channel L = 30 nm OFET as observed by Japanese Research Group [1] is depicted in the figure. Now, before going into detail discussion on nanoOFETs, it is necessary to understand the transport behavior in long channel OFETs. OFETs with channel length (L) less than 1 um is termed as nanoOFETs. In such OFETs, when gate-potential is sufficiently larger than the drain-potential, transitor output current saturates. However, in nanoOFETs, transistor fails to produce saturated output current. In other words, output current changes non-linearly with drain-potential. In this section, two major short-channel behavor in L = 70 nm OFET is discussed in detail, which includes: non-saturating behavior and lowering of gate effect in nanoOFETs.



Surface Analysis of P3HT Organic Semiconductor

The section deals with the surface analysis of thin film of P3HT organic semiconductor (45 nm) deposited on the silicon wafer. AFM measurements are made on such film of semiconductor. AFM pictures reveal that the film of P3HT gives homogeneously distributed individual crystalline grain like structures. Interestingly, the size of the grain increases with increasing P3HT concentration (also film thickness). Futher, the average grain size is calculated with Gwyddion software applying grain-correlation standard library package. The software applies water-shed algorithm to the grains producing average disc radius. The average grain size of 0.5 wt. % of 45 nm thin film of P3HT P200 semiconductor deposited on clean silicon wafer (above the oxide layer) is calculated to be 150 nm.









Introduction to ALD Process

ALD of Alumina (Al2O3) on SiO2

ALD Surface Reaction: An Overview

⇒ Magnetic Memory Unit


Single Molecular Rectifiers




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Last Updated on July 14th, 2012 at 19:00 pm